1. Field of the Invention
The present invention relates generally to anti-fuse devices and anti-fuse structures, as employed when fabricating microelectronic fabrications. More particularly, the present invention relates to anti-fuse devices and anti-fuse structures with comparatively low programming voltage, as employed when fabricating microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers that are separated by microelectronic dielectric layers.
In addition to conventional microelectronic devices and microelectronic structures that are employed when fabricating microelectronic fabrications, including but not limited to conventional microelectronic transistor devices and conventional microelectronic transistor structures, conventional microelectronic resistor devices and conventional microelectronic resistor structures, conventional microelectronic capacitor devices and conventional microelectronic capacitor structures and conventional microelectronic diode devices and conventional microelectronic diode structures that are employed when fabricating microelectronic fabrications, microelectronic anti-fuse devices and microelectronic anti-fuse structures are also of interest for use when fabricating microelectronic fabrications.
Microelectronic anti-fuse devices and microelectronic anti-fuse structures are of interest for use when fabricating microelectronic fabrications insofar as microelectronic anti-fuse devices and microelectronic anti-fuse structures often provide cost effective microelectronic devices and microelectronic structures that may be employed for functions within microelectronic fabrications including but not limited to redundant circuit programming functions within microelectronic fabrications, as well as microelectronic fabrication product identification functions within microelectronic fabrications.
While microelectronic anti-fuse devices and microelectronic anti-fuse structures are thus of interest for use when fabricating microelectronic fabrications and are often invaluable for use when economically fabricating various types of microelectronic fabrications, microelectronic anti-fuse devices and microelectronic anti-fuse structures are nonetheless not entirely without problems in the art of microelectronic fabrication. In that regard, microelectronic anti-fuse devices and microelectronic anti-fuse structures when fabricated within microelectronic fabrications are often difficult to electrically actuate to provide electrically conductive fused microelectronic anti-fuse devices and electrically conductive fused microelectronic anti-fuse structures without in turn electrically over-stressing adjacent microelectronic devices and adjacent microelectronic structures within the microelectronic fabrications within which are fabricated the microelectronic anti-fuse devices and the microelectronic anti-fuse structures.
It is thus desirable in the art of microelectronic fabrication to provide methods and materials for fabricating within microelectronic fabrications microelectronic anti-fuse devices and microelectronic anti-fuse structures which upon electrical actuation minimally electrically stress adjacent microelectronic devices and adjacent microelectronic structures within the microelectronic fabrications within which are fabricated the microelectronic anti-fuse devices and the microelectronic antifuse structures.
It is towards the foregoing object that the present invention is directed.
Various microelectronic fabrication devices and microelectronic fabrication structures having desirable properties, including but not limited to microelectronic anti-fuse devices and microelectronic anti-fuse structures having desirable properties, have been disclosed in the art of microelectronic fabrication.
For example, Yamaoka et al., in U.S. Pat. No. 5,946,575, discloses a microelectronic anti-fuse structure and a method for fabricating the microelectronic anti-fuse structure, where there is independently maintained an integrity of electrical properties of a pair of adjoining microelectronic devices fabricated within the microelectronic anti-fuse structure. To realize the foregoing object the microelectronic anti-fuse structure comprises a pair of adjoining metal oxide semiconductor field effect transistor (MOSFET) devices formed within and upon a single silicon substrate layer, where a higher breakdown voltage metal oxide semiconductor field effect transistor (MOSFET) device within the pair of metal oxide semiconductor field effect transistor (MOSFET) devices employs a thicker gate dielectric layer and a lower semiconductor substrate channel doping concentration in comparison with a lower breakdown voltage metal oxide semiconductor field effect transistor (MOSFET) device within the pair of metal oxide semiconductor field effect transistor (MOSFET) devices.
In addition, Iyer et al., in U.S. Pat. No. 6,096,580, discloses a method for fabricating, with a comparatively low programming voltage, a microelectronic anti-fuse device that may be employed within a microelectronic anti-fuse structure that in turn may be employed within a microelectronic fabrication. To realize the foregoing object, the method employs ion implanting into: (1) a gate dielectric layer within a metal oxide semiconductor field effect transistor (MOSFET) microelectronic anti-fuse device; or (2) a capacitive dielectric layer within a metal oxide semiconductor (MOS) capacitor microelectronic anti-fuse device, a dose of a comparatively heavy implanting ion, such as a comparatively heavy indium implanting ion, such as to provide the metal oxide semiconductor field effect transistor (MOSFET) microelectronic anti-fuse device or the metal oxide semiconductor (MOS) capacitor microelectronic anti-fuse device with the comparatively low programming voltage.
Finally, Candelier et al., in xe2x80x9cOne Time Programmable Drift Antifuse Cell Reliability,xe2x80x9d IEEE 38th Annual International Reliability Physics Symposium, San Jose, Calif., 2000, pp 169-73, discloses a microelectronic anti-fuse structure that may be employed within a microelectronic fabrication, wherein the microelectronic anti-fuse structure may be fabricated employing methods as are fully compatible with complementary metal oxide semiconductor (CMOS) fabrication methods otherwise employed for fabricating the microelectronic fabrication. To realize the foregoing object, the microelectronic anti-fuse structure comprises a metal oxide semiconductor (MOS) capacitor microelectronic anti-fuse device fabricated electrically in series with a drift N-metal oxide semiconductor field effect transistor (MOSFET) device.
Desirable in the art of microelectronic fabrication are additional microelectronic anti-fuse devices and microelectronic anti-fuse structures which upon electrical actuation minimally electrically stress adjacent microelectronic devices and adjacent microelectronic structures within the microelectronic fabrications within which are fabricated the microelectronic anti-fuse devices and the microelectronic anti-fuse structures.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide for use when fabricating a microelectronic fabrication an anti-fuse structure and a method for operating the anti-fuse structure.
A second object of the present invention is to provide the anti-fuse structure and the method for operating the anti-fuse structure in accord with the first object of the present invention, where upon electrical actuation of the anti-fuse structure there is minimally electrically stressed adjacent microelectronic devices and adjacent microelectronic structures within the microelectronic fabrication within which is fabricated the microelectronic anti-fuse structure.
A third object of the present invention is to provide an anti-fuse structure and a method for fabricating the anti-fuse structure in accord with the first object of the present invention and the second object of the present invention, where the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention an anti-fuse structure for use when fabricating a microelectronic fabrication and a method for operating the anti-fuse structure for use when fabricating the microelectronic fabrication.
The anti-fuse structure of the present invention comprises in a first instance a semiconductor substrate having a first region adjoining a second region. In addition, the anti-fuse structure of the present invention also comprises a metal oxide semiconductor field effect transistor (MOSFET) device formed within and upon the first region of the semiconductor substrate and a metal oxide semiconductor (MOS) capacitor device formed within and upon the second region of the semiconductor substrate. Finally, within the anti-fuse structure of the present invention: (1) a gate dielectric layer within the metal oxide semiconductor field effect transistor (MOS) device is thicker than a capacitive dielectric layer within the metal oxide semiconductor (MOS) capacitor device; and (2) the metal oxide semiconductor (MOS) capacitor device employs as a first capacitor plate a doped well within the semiconductor substrate of equivalent polarity with and overlapping with a source/drain region within the metal oxide semiconductor field effect transistor (MOSFET) device.
The anti-fuse structure of the present invention contemplates at least one method for forming the anti-fuse structure of the present invention, as well as a method for operating the anti-fuse structure of the present invention.
The present invention provides, for use when fabricating a microelectronic fabrication, an anti-fuse structure and a method for operating the anti-fuse structure, where upon electrical actuation of the anti-fuse structure there is minimally electrically stressed adjacent microelectronic devices and adjacent microelectronic structures within the microelectronic fabrication within which is fabricated the anti-fuse structure. The anti-fuse structure of the present invention realizes the foregoing object by employing within the anti-fuse structure as formed within and upon a semiconductor substrate: (1) a metal oxide semiconductor field effect transistor (MOSFET) device; and (2) a metal oxide semiconductor (MOS) capacitor device, where: (1) a gate dielectric layer within the metal oxide semiconductor field effect transistor (MOSFET) device is thicker than a capacitive dielectric layer within the metal oxide semiconductor (MOS) capacitor device; and (2) the metal oxide semiconductor (MOS) capacitor device employs as a first capacitor plate a doped well within the semiconductor substrate of equivalent polarity with and overlapping with a source/drain region within the metal oxide semiconductor field effect transistor (MOSFET) device.
The method of the present invention is readily commercially implemented. As will be illustrated in greater detail within the Description of the Preferred Embodiment, as set forth below, an anti-fuse structure fabricated and operated in accord with the present invention may be fabricated and operated employing methods and materials as are otherwise generally known in the art of microelectronic fabrication, but employed at least in part with a specific ordering to provide an anti-fuse structure with specific structural characteristics and operational characteristics in accord with the present invention. Since it is thus a specific ordering of methods and materials that provides at least in part the present invention, rather than the existence of specific methods and materials that provides the present invention, the method of the present invention is readily commercially implemented.